| OUTPUT LOGIC FORM | TRANSISTOR-TRANSISTOR LOGIC |
| MAXIMUM POWER DISSIPATION RATING | 137.0 MILLIWATTS |
| TEST DATA DOCUMENT | 81349-MIL-M-38510 SPECIFICATION (INCLUDES ENGINEERING TYPE BULLETINS, BROCHURES,ETC., THAT REFLECT SPECIFICATION TYPE DATA IN SPECIFICATION FORMAT; EXCLUDES COMMERCIAL CATALOGS, INDUSTRY DIRECTORIES, AND SIMILAR TRADE PUBLICATIONS, REFLECTING GENERAL TYPE DATA ON CERTAIN ENVIRONMENTAL AND PERFORMANCE REQUIREMENTS AND TEST CONDITIONS THAT ARE SHOWN AS "TYPICAL", "AVERAGE", "NOMINAL", ETC.). |
| TIME RATING PER CHACTERISTIC | 13.00 NANOSECONDS MAXIMUM PROPAGATION DELAY TIME, LOW TO HIGH LEVEL OUTPUT AND 13.00 NANOSECONDS MAXIMUM PROPAGATION DELAY TIME, HIGH TO LOW LEVEL OUTPUT |
| VOLTAGE RATING AND TYPE PER CHARACTERISTIC | 7.0 VOLTS MAXIMUM POWER SOURCE |
| SPECIFICATION/STANDARD DATA | 81349-MIL-M-38510/71 GOVERNMENT SPECIFICATION |
| STORAGE TEMP RANGE | -65.0/+150.0 DEG CELSIUS |
| TERMINAL TYPE AND QUANTITY | 16 FLAT LEADS |
| TERMINAL SURFACE TREATMENT | SOLDER |
| BODY HEIGHT | 0.045 INCHES MINIMUM AND 0.085 INCHES MAXIMUM |
| BODY LENGTH | 0.440 INCHES MAXIMUM |
| BODY WIDTH | 0.245 INCHES MINIMUM AND 0.285 INCHES MAXIMUM |
| CASE OUTLINE SOURCE AND DESIGNATOR | F-5 MIL-M-38510 |
| DESIGN FUNCTION AND QUANTITY | 2 FLIP-FLOP, J-K |
| FEATURES PROVIDED | HERMETICALLY SEALED AND MONOLITHIC AND SCHOTTKY AND EDGE TRIGGERED AND W/CLEAR AND W/CLOCK AND W/PRESET |
| INCLOSURE CONFIGURATION | FLAT PACK |
| INCLOSURE MATERIAL | CERAMIC AND GLASS |
| INPUT CIRCUIT PATTERN | DUAL 5 INPUT |
| OPERATING TEMP RANGE | -55.0/+125.0 DEG CELSIUS |